Low Power FPGA-based Hardware Accelerator for Autonomous Navigation of Mobile Robots

Abstract

Power consumption is an important parameter in designing autonomous mobile robots (AMR), especially for time-constrained applications. Most AMRs use battery power for navigation and as a result, the runtime of such robots is often limited. Conventional power optimization techniques frequently put constraints to robot motion and limit the freedom of navigation. In this work, we propose an FPGA-based hardware accelerator to optimize power consumption with high performance in the navigational computations. Simulation and experiment results show that the hardware accelerator consumes x4.12 less power and improves Power-Delay-Product by x12.35 compared to the state-of-the-art implementation.