Research

Low Power FPGA-based Hardware Accelerator for Autonomous Navigation of Mobile Robots

Power consumption is an important parameter in designing autonomous mobile robots (AMR), especially for time-constrained applications. Most AMRs use battery power for navigation and as a result, the runtime of such robots is often limited. In this work, I developed a hardware-software co-design architecture to optimize power consumption with high performance in navigational computations. The FPGA hardware accelerator is designed for the forward simulation part of the local planner of the ROS navigation stack and picking the best velocity command is implemented in the ARM processor in C++. Exploiting the possibilities of parallel computations in FPGA, multiple trajectories are simulated in parallel thus reducing computation time as well. Simulation and experiment results show that the resulting component is consuming less power to a degree of four and faster.

K. Senthurbavan, Peshala Jayasekara & Dilan Weerakkody. “Low Power FPGA-based Hardware Accelerator for Autonomous Navigation of Mobile Robots”. In 2020 Australasian Conference on Robotics and Automation (ACRA 2020) (Paper link)

Overview of the system:


Overview of the hardware accelerator:


Demonstration video: